Prior art MOSFETs include a source and a drain formed in an active region of a semiconductor layer (semiconductor-on-insulator or “SOI” format) or of a semiconductor body (bulk format) by implanting appropriate impurities therein. Between the source and the drain resides a so-called channel (or body) region. A gate resides on the semiconductor above the channel region. The gate comprises a gate electrode and a dielectric layer. The gate electrode is spaced from the semiconductor by the gate dielectric layer. Application of appropriate electrical signals to the gate electrode selectively permits or prevents electrical conduction between the source and the drain.
On-going attempts are being made to decrease the size of MOSFETs and/or to increase their speed of operation, while investing them with greater electrical reliability. These attempts have involved such techniques as: forming ultra-shallow junctions while increasing dopant activation so that sheet resistance in the channel region does not increase; using epitaxial techniques to form high-dopant sources and drains and to form high-dopant extensions of the sources and the drains to reduce resistance at the semiconductor-source/drain interfaces; using epitaxial techniques to achieve appropriate compressive or tensile stresses in the channel; and using thin layers of high-k materials, i.e., materials having a dielectric constant (or relative permittivity) greater than about 3.9, as gate dielectrics—instead of typical oxide layers having dielectric constants of about 3.9 or less—to prevent gate tunneling leakage between the gate electrode and the channel region.
Following fabrication of the above-described smaller, faster MOSFETs using epitaxial techniques to form the source and drain and having a thin gate oxide, damage to the gate oxide has been detected. Such damage causes gate-electrode-to-source-extension bridging or gate-electrode-to-drain-extension bridging. It is postulated that such damage is caused by the processes typically effected prior to and during the epitaxial steps carried out to produce the source, the drain and their extensions. Such damage gives rise to excessive gate leakage current and device failure following formation of the selective epitaxy source and drain and/or their extensions.
The present invention eliminates or ameliorates prior art problems related to the fabrication of USJ MOSFETs having in-situ doped selective epitaxy source/drain extensions and high-k gate dielectrics, including problems such as unacceptable gate leakage currents, gate-to-source-extension bridging and gate-to-drain-extension bridging, low dopant activation, and high sheet resistance of the source/drain extensions.